Synopsys, Inc. has announced a series of major technology milestones achieved in partnership with TSMC, aimed at accelerating the development of next-generation artificial intelligence (AI), high-performance computing (HPC), and advanced semiconductor systems.
Through the integration of AI-powered Electronic Design Automation (EDA) flows, multiphysics-aware signoff methodologies, multi-die design frameworks, and silicon-proven Interface and Foundation IP, the two semiconductor leaders are lowering the barriers to complex silicon development. The expanded collaboration directly supports accelerated adoption of TSMC’s latest process nodes and advanced packaging architectures.
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“As AI systems continue to grow in scale and complexity, customers require proven IP, intelligent design solutions, and advanced packaging methodologies that work together seamlessly,” said Michael Buehler-Garcia, Senior Vice President at Synopsys. “Our joint innovations with TSMC address the continuum of silicon to systems co-design capabilities needed to accelerate development of next-generation AI and high-performance computing systems.”
“Our collaboration with Open Innovation Platform® (OIP) ecosystem partners like Synopsys continues to meet the rapidly growing demands of AI and high-performance computing,” said Aveek Sarkar, Director of the Ecosystem and Alliance Management Division at TSMC. “By combining certified EDA solutions and silicon-proven IP portfolio from Synopsys with our latest process and packaging innovations, we are enabling customers to push the boundaries of performance, integration, and energy efficiency to shape the future of AI.”
Streamlining Advanced-Node Adoption with Certified Flows
To help engineering teams transition smoothly to cutting-edge nodes, Synopsys achieved EDA certification across both digital and analog flows for the TSMC A14 process. The joint effort incorporates agentic AI capabilities to deliver an end-to-end implementation-to-signoff methodology, speeding up design convergence for complex semiconductors.
In parallel, the partners completed device routing enablement on TSMC A14 within the analog domain. This capability unlocks enhanced place-and-route automation, improving layout efficiency and reducing time-to-market for advanced analog designs.
Enhancing Productivity Through Agentic AI Workflows
Automation and designer autonomy take center stage with the deployment of agentic AI across analog, digital, and heterogeneous multi-die engineering paths.
- Analog & Digital Migration: The Synopsys Custom Compiler™ platform facilitates faster analog migration, while Fusion Compiler™ leverages large language model (LLM) analysis to boost digital optimization productivity.
- Chiplet Co-Optimization: To simplify complex heterogeneous multi-die architectures, the Synopsys 3DIC Compiler platform now features an agentic AI floorplanning flow. This automated system optimizes floorplan configurations for TSMC 3DFabric® technologies, driving faster design closure.
Advancing Multi-Die Power Integrity and Optical Interconnects
As power requirements intensify across massive AI workloads, Integrated Voltage Regulators (IVRs) have become essential for maintaining power efficiency in multi-die environments. Designers can now utilize the Synopsys 3DIC Compiler platform to co-design and simulate IVRs directly on TSMC CoWoS® packaging within a single unified environment.
Additionally, Synopsys and TSMC are addressing data-transfer bottlenecks by advancing co-packaged optics (CPO) on TSMC COUPE™ technology. Their co-design solution merges electronic and photonic engineering workflows spanning 3DIC setup, multiphysics verification, and layout optimization to help mutual customers implement fast, reliable optical interconnects.
Expanding the Silicon-Proven IP Portfolio for AI and HPC
Underpinning the joint enablement effort is an expanded suite of silicon-proven Interface, Foundation, and Silicon Lifecycle Management (SLM) IP engineered specifically for TSMC’s advanced nodes.
Key highlights include:
- TSMC N2P Milestones: Synopsys achieved significant IP tape-out milestones on the N2P node, encompassing critical AI and data center standards such as PCIe 7.0, HBM4, LPDDR6/5X/5, 224G Ethernet PHY, UCIe, OTP, and real-time process, voltage, and temperature (PVT) monitoring IP.
- Die-to-Die Validation: Demonstrating multi-die progress, Synopsys successfully validated UCIe-A 32G/40G silicon on a TSMC N3P test chip paired with a CoWoS-S interposer. Furthermore, 64G UCIe IP tape-outs featuring embedded design-for-test (DFT) diagnostic capabilities were recently completed on both 2nm and 3nm nodes.
- Broad Ecosystem Enablement: IP availability was also expanded across TSMC N3P, N2P, and compact “C” process nodes (spanning 6nm to 3nm), providing lower power consumption and higher integration density for applications ranging from automotive and mobile to edge AI and enterprise networking.
