Partnership strengthens AlphaWave Semi’s PCIe 6.0 PHY and controller solutions through third-party validation and improves interoperability across AI compute infrastructures
AlphaWave Semi is a global leader in providing high-speed connectivity for the world’s technology infrastructure. Announcing a partnership with Keysight Technologies, a market leader in solutions, to integrate AlphaWave Semi’s PCIe 6.0 64 GT/s subsystem (PHY and controller) devices with the Keysight PCIe 6.0 64 GT/s protocol exerciser. We demonstrated operability and successfully negotiated links at maximum PCIe 6.0 data rates. AlphaWave Semi is already on the PCI-SIG 5.0 integrator list and is accelerating next-generation PCIe 6.0 compliance testing through this partnership.
AlphaWave Semi’s advanced silicon implementation of the new PCIe 6.0 64 GT/s Flow Control Unit (FLIT)-based protocol enables high data rates for hyperscale data infrastructure applications. Keysight and his AlphaWave Semi also successfully established CXL 2.0 links to set up future cache coherency in the data center.
Letigia Giuliano, Vice President of IP Product Marketing at AlphaWave Semi, said: “Test and measurement is a critical element of interoperability, which allows AlphaWave Semi to bring products and customer solutions to market faster. We are excited to partner with Keysight. This accelerates the transition to 64 GT/s using Keysight’s state-of-the-art PCIe 6.0 protocol validation solution, further ensuring consistency in connectivity solutions that accelerate AI processing in high-performance computing and data infrastructure. can be provided.
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said Dr. Joachim Peerlings, Vice President of Network and Data Center Solutions at Keysight. “PCIe will play a critical role in connecting compute resources and efficiently processing the required workloads as AI expands. Demonstrates both companies’ commitment to developing the PCIe 6.0 standard in anticipation of demand for high-performance computing, which will enable new connectivity to address the surge in I/O performance required for compute-intensive applications such as generative AI. The era has arrived.”
With PCIe 6.0, the universal technology evolves from 2-level NRZ to 4-level PAM4 signals. While this transition poses challenges for signal integrity and new protocols to ensure critical backwards compatibility, it also future-proofs the technology through the implementation of forward error correction (FEC) over FLIT. FEC enables higher bit error rates (BER) with acceptable packet loss. This partnership resulted in successful FLIT mode transactions (requests and completions) for payload FLIT in the silicon implementation of the PCIe 6.0 64 GT/s subsystem.
AlphaWave Semi’s PCIe subsystem is built on the industry’s most successful PAM4 SerDes IP, an extremely low power, low latency, and highly reliable interface IP. For AI and high-performance computing (HPC) systems where memory performance is critical, AlphaWave Semi’s PCIe 6.0 subsystem supports PCIe and CXL controllers and enables memory consistency at the data center level. You can extend CXL 3.0 to
For more information about AlphaWave Semi’s IP portfolio, please visit AlphaWave Semi‘s PCI-Express and CXL Solutions
Keysight’s recently introduced PCIe 6.0 protocol analysis accelerates testing and significantly improves signal integrity in a slim form factor.
SOURCE: BusinessWire
