Synopsys, announced its continued strategic collaboration with TSMC to advance multi-die solutions through cutting-edge EDA and IP products. These solutions support TSMC’s leading-edge processes and packaging technologies, enabling breakthrough innovation in AI chip design and multi-die integration. Synopsys’ 3DIC Compiler exploration-to-signoff platform, optimized for 3D packaging, coupled with the company’s design enablement partnership with TSMC, has already facilitated multiple successful customer tape-outs.
The collaboration further extends to certified digital and analog flows, as well as Synopsys.ai™ support on TSMC’s N2P and A16™ processes via TSMC NanoFlex™ architecture. Synopsys also delivers advanced automotive IP for TSMC N5A and N3A nodes, along with industry-leading Interface and Foundation IP solutions. These offerings ensure the highest levels of safety, security, and reliability, while maximizing performance and minimizing power consumption for next-generation semiconductor designs.
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“Our close collaboration with TSMC continues to empower engineering teams to achieve successful tape outs on the industry’s most advanced packaging and process technologies,” said Michael Buehler-Garcia, Senior Vice President at Synopsys. “With certified digital and analog EDA flows, 3DIC Compiler platform, and our comprehensive IP portfolio optimized for TSMC’s advanced technologies, Synopsys is enabling mutual customers to deliver differentiated multi-die and AI designs with enhanced performance, lower power, and accelerated time to market.”
“TSMC has been working closely with our long-standing Open Innovation Platform® (OIP) ecosystem partners like Synopsys to help customers achieve high quality-of-results and faster time-to-market for leading-edge SoC designs,” said Aveek Sarkar, Director of the Ecosystem and Alliance Management Division at TSMC. “With the ever-growing need for energy efficient and high-performance AI chips, the OIP ecosystem collaboration is crucial for providing our mutual customers with certified EDA tools, flows and high-quality IP to meet or exceed their design targets.”
Optimized EDA Flows for Advanced TSMC Processes
Synopsys’ analog and digital flows, including Synopsys.ai, are certified on TSMC N2P and A16™ processes, leveraging the NanoFlex™ architecture to optimize chip performance, power, and scalability. Certified capabilities for TSMC A16™ Super Power Rail (SPR) enhance power distribution and system performance while maintaining thermal robustness in backside routing designs. The company’s pattern-based pin access methodology has been updated for the A16™ node to deliver superior area results. Synopsys is also collaborating with TSMC on design flow development for the upcoming A14 process, with the first process design kit expected in late 2025.
Synopsys IC Validator™ signoff solution is certified for TSMC A16™, supporting DRC and LVS verification. Its high-capacity elastic architecture efficiently scales PERC rules for TSMC’s N2P full-path electrostatic discharge (ESD) checks, improving turnaround times.
Advanced 3D Integration and CoWoS® Technologies
The 3DIC Compiler platform supports TSMC-SoIC® (SoIC-X) technology, enabling 3D stacked designs and silicon interposer integration with CoWoS® technologies. Customers benefit from enhanced productivity and faster turnaround through automated UCIe and HBM routing, TSV and bump planning, and multi-die signoff verification.
Synopsys and TSMC are also advancing AI-optimized photonic IC flows via TSMC-COUPE™ technology, delivering improved system performance while addressing multi-wavelength and thermal requirements for multi-die and AI designs.
Comprehensive IP Portfolio Accelerates Semiconductor Innovation
Synopsys’ extensive portfolio of Foundation and Interface IP supports TSMC’s N2P/N2X nodes, enabling high-performance standards such as HBM4, 1.6T Ethernet, UCIe, PCIe 7.0, and UALink. The portfolio includes proven PHYs, embedded memories, high-density logic libraries, programmable IO, and NVM IP. Specialized IP for automotive N5A and N3A nodes, along with advanced SRAM and Foundation IP for 5nm and 3nm SoCs, allows customers to meet the demanding requirements of next-generation designs across AI, HPC, automotive, and IoT markets.
