Synopsys, Inc. announced the industry’s first complete PCIe 7.0 IP solution consisting of controller, IDE security module, PHY, and verification IP. This solution will enable chip makers to address the demanding bandwidth and latency requirements of transferring massive amounts of data for compute-intensive AI workloads while supporting broad ecosystem interoperability. Large language models’ demand for computational capabilities is growing at a breakneck pace, with trillions of parameters needing to be processed in data centers as fast and reliably as possible. Synopsys offers the industry’s only PCIe standards-based solution for secure data transfers up to 512 GB/s bidirectional in a x16 configuration to mitigate AI workload data bottlenecks. Synopsys will demonstrate this world’s first technology at PCI-SIG DevCon in Santa Clara on June 12 and 13, 2024.
“As the leading provider of interface IP, Synopsys continues to give designers access to the latest interfaces in the most advanced nodes, helping them to address the demands of compute-intensive designs,” said John Koeter, senior vice president of marketing and strategy for IP, Synopsys. “Synopsys’ IP for PCI Express 7.0 will provide customers with a complete, standards-based solution enabling an early start on next generation of HPC and AI designs and accelerating the path to silicon success.”
World’s First PCIe 7.0 IP Over Optics Demo at PCI-SIG Developers Conference 2024
Synopsys will feature two world’s first demonstrations at the PCI-SIG Developers Conference on June 12 and 13, 2024: Synopsys PCI Express 7.0 PHY IP electrical-optical-electrical (E-O-E) TX to RX running at 128 Gb/s with OpenLight’s Photonic IC, and Synopsys PCIe 7.0 Controller IP showing a successful root complex to endpoint connection with FLIT transfer. In addition, Synopsys will showcase its PCIe 7.0 IP ecosystem interoperability with multiple partners, including Keysight Technologies, Samtec, and Teledyne LeCroy.
Industry’s First Complete Synopsys PCIe 7.0 IP Solution
Synopsys’ IP solution for PCIe 7.0, including controller, IDE security module, PHY and verification IP, reduces integration risk for AI and HPC networking chips. The IP solution, compliant to evolving standards, improves interconnect power efficiency by up to 50% and enables twice the interconnect bandwidth for the same chip perimeter compared to prior PCIe generations. Synopsys PCIe 7.0 Controller IP enables low latency, high-bandwidth links with a full endpoint to root-complex solution that supports all required features for backward compatibility. Synopsys PCIe 7.0 PHY IP provides excellent signal integrity with speeds up to 128 Gb/s per lane, and seamlessly integrates with Synopsys CXL Controller IP solutions. Synopsys Integrity and Data Encryption (IDE) Security IP for PCIe 7.0 provides confidentiality, integrity, and replay protection against hardware-level attacks. Synopsys PCIe 7.0 Verification IP and hardware-assisted verification solutions offer built-in protocol checks and multiple configurations of controller and PHY to accelerate verification and validation closure.
Broad Portfolio of Synopsys IP for High-Performance Computing
Synopsys offers the industry’s broadest high-speed interface IP portfolio for high-performance computing SoC designs, including complete, secure IP solutions for PCIe 7.0, 1.6T/800G Ethernet, CXL, and HBM. With Synopsys’ extensive interoperability testing, comprehensive technical support, and robust IP performance, designers can accelerate time to silicon success and production.
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Industry Leaders Embrace PCIe 7.0 for AI Data Center Infrastructure
The new Synopsys PCIe 7.0 IP solution is backed by leading companies to meet the market demand for advanced, trusted interconnects that enable engineering teams to start their next generation of HPC and AI chip designs with confidence.
“Accelerating every interconnect within the data center, including PCI Express, is critical to address the performance demands of AI clusters at scale,” said Debendra Das Sharma, Senior Fellow and Chief I/O Architect at Intel Corporation. “The combination of Synopsys IP for PCIe 7.0 and Intel’s future generation products will offer system architects both the bandwidth needed for the most demanding data center workloads and seamless ecosystem integration.”
“PCI Express is at the core of our portfolio of purpose-built connectivity solutions that are used by all major hyperscalers and AI platform providers,” said Casey Morrison, Chief Product Officer, Astera Labs. “PCIe 7.0 is essential to deliver a 2x bandwidth boost at minimal latency which are both critical goals for rapidly evolving Generative AI and high-performance computing applications. We applaud Synopsys for being at the forefront of enabling the PCIe 7.0 ecosystem.”
“PCI Express technology has been essential to the evolution, performance, and interoperability of modern data center server I/O,” said Rochan Sankar, President and CEO, Enfabrica. “Enfabrica’s Accelerated Compute Fabric silicon can leverage Synopsys’ PCIe 7.0 IP and deliver highly integrated, reliable, and performant scale-up / scale-out interconnect to everyone building next-generation AI compute infrastructure.”
“To enable deep learning and AI workloads, hyperscalers need reliable, industry-standard interfaces that provide high-performance, low latency connectivity,” said Amin Shokrollahi, CEO, Kandou. “With Kandou’s PCIe retimers and Synopsys’ PCIe 7.0 IP, system designers will be enabled with high-bandwidth, secure connections, which are critical for data-intensive, latency-sensitive workloads.”
“Data center disaggregation and evolving server architectures need wide ecosystem interoperability to move massive amounts of data efficiently,” said Gerry Fan, CEO, XConn. “XConn’s PCIe/CXL switches and Synopsys’ new PCIe 7.0 IP will be key for these emerging architectures applications, enabling deployment at scale of high-performance, standards-compliant systems.”
“To train large language models, immense volumes of data must be processed faster than ever. PCI Express 7.0 enables scaling high-bandwidth, secure and low latency interconnects to meet tomorrow’s AI data demands,” said Mark Hayter, Founder and Chief Strategy Officer, Rivos. “Rivos RISC-V based AI system solutions with the most advanced interfaces, like Synopsys IP for PCIe 7.0, enable system architects to achieve power efficient, high performance and secure connectivity, critical to deliver the next generation of chips for AI workloads.”
“Microchip is dedicated to advancing high-performance computing and artificial intelligence technologies,” stated Bob Divivier, Appointed Vice President of Microchip’s Data Center Solutions business unit. “Incorporating Synopsys’ advanced PCIe 7.0 IP solution into our next-generation PCIe product line will empower system architects to harness significantly enhanced levels of bandwidth and efficiency in high-level HPC and AI applications.”
“With its high bandwidth and low latency, PCIe 7.0 will provide AI data center infrastructure a dramatic leap in performance,” said Matthew Burns, Global Director, Technical Marketing at Samtec. “To help enable the ecosystem and give designers access to early testing, Samtec and Synopsys will demonstrate interoperability testing at PCI-SIG DevCon 2024, showcasing the long-reach performance results of Samtec’s NovaRay® I/O panel mount cable system, NovaRay® cable system, and the Synopsys‘ PCI Express 7.0 IP. Samtec’s extensive line of high-performance interconnect systems provide the thermal efficiencies, small form factors, extreme data rates and density, and signal integrity optimized performance required to avoid bottlenecks in current and next-generation data center applications.”
Source: PRNewswire
