Marvell Technology, Inc, a leader in data infrastructure semiconductor solutions, announced the advancement of its custom XPU architecture with co-packaged optics (CPO) technology. Building on its recently announced custom high-bandwidth memory (HBM) compute architecture, Marvell is now extending its custom silicon leadership by enabling customers to seamlessly integrate CPO into their next-generation custom XPUs and scale-up the size of their AI servers from tens of XPUs within a rack currently using copper interconnects to hundreds across multiple racks using CPO, enhancing AI server performance. The innovative architecture enables cloud hyperscalers to develop custom XPUs that achieve higher bandwidth density and deliver longer reach XPU-to-XPU connections within a single AI server – with optimal latency and power efficiency. The architecture is now available for Marvell customers’ next-generation custom XPU designs.
The Marvell custom AI accelerator architecture combines XPU compute silicon, HBM and other chiplets with Marvell 3D SiPho Engines on the same substrate using high-speed SerDes, die-to-die interfaces and advanced packaging technologies. This approach eliminates the need for electrical signals to leave the XPU package into copper cables or across a printed circuit board. With integrated optics, connections between XPUs can achieve faster data transfer rates and distances that are 100X longer than electrical cabling. This enables scale-up connectivity within AI servers that spans multiple racks with optimal latency and power dissipation.
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CPO technology integrates optical components directly within a single package, minimizing the electrical path length. This close coupling significantly reduces signal loss, enhances high-speed signal integrity, and minimizes latency. CPO enhances data throughput by leveraging high-bandwidth silicon photonics optical engines, which provide higher data transfer rates and are less susceptible to electromagnetic interference compared to traditional copper connections. This integration also improves power efficiency by reducing the need for high-power electrical drivers, repeaters and retimers. By enabling longer reach and higher density XPU-to-XPU connections, CPO technology facilitates the development of high-performance, high-capacity scale-up AI servers, optimizing both compute performance and power consumption for next-generation accelerated infrastructure.
First demonstrated at OFC 2024, the industry-first Marvell 3D SiPho Engine – which supports 200Gbps electrical and optical interfaces – is a fundamental building block for incorporating CPO into XPUs. The Marvell 6.4T 3D SiPho Engine is a highly integrated optical engine with 32 channels of 200G electrical and optical interfaces, hundreds of components such as modulators, photodetectors, modulator drivers, trans-impedance amplifiers, microcontrollers, and a host of other passive components in a single, unified device to deliver 2x the bandwidth, 2x the input/output bandwidth density, and 30% lower power per bit versus comparable devices with 100G electrical and optical interfaces. Multiple customers are evaluating the technology for integration into their next-generation solutions.
For more than eight years, Marvell has delivered silicon photonics technology for successive generations of high-performance, low power COLORZ® data center interconnect optical modules. This technology has been qualified and deployed in high-volume production by numerous leading hyperscalers to satisfy their growing data center to data center bandwidth needs. Marvell silicon photonics devices have logged over 10 billion field hours.
SOURCE: PRNewswire
