Synopsys, Inc. kicked off its annual flagship Synopsys User Group (SNUG) conference in Silicon Valley at the Santa Clara Convention Center with a keynote presentation by Synopsys president and CEO Sassine Ghazi. Ghazi discussed the unprecedented innovation opportunities and challenges that technology R&D teams face in this era of pervasive intelligence. He also announced new EDA and IP solutions aimed at maximizing the capabilities of the global technology engineering teams, from silicon to systems, that Synopsys serves.
“The rapid advancement of AI, silicon proliferation, and software-defined systems are driving the era of pervasive intelligence, where technology is seamlessly integrated into our lives, bringing with it unprecedented opportunity and greater compute, energy, and design challenges for the technology industry,” said Ghazi. “Synopsys is committed to collaborating with the ecosystem to address these challenges, while delivering the trusted silicon to systems design solutions our customers need to expand R&D capacity, maximize productivity, and power their innovations for this new era.”
Jensen Huang, founder and CEO of NVIDIA, joined Ghazi on stage and discussed the companies’ shared history of innovation, impact of AI on the semiconductor industry, and newly announced technology collaborations. Today’s events also featured video commentary from additional customers and partners including AMD, Ampere, Arm, Astera Labs, Intel Foundry Services, Microsoft, Tesla, TSMC, and Samsung who each explained the important role Synopsys plays in their success.
Below is a summary of Synopsys technology news and announcements made during today’s keynote presentation.
Synopsys.ai Gains Momentum: Synopsys DSO.ai and VSO.ai Delivering Stunning Customer Results
Today’s keynote showcased the strong momentum for Synopsys.ai, the company’s AI-driven full-stack EDA suite. Ghazi said Synopsys.ai usage is expanding rapidly, led by DSO.ai, Synopsys’ industry-first AI application for optimizing layout implementation workflows, and VSO.ai, the industry-first, AI-driven verification solution.
Ghazi said Synopsys.ai has achieved hundreds of tape-outs to date and is delivering stunning customer results including a more than 10% boost in performance, power, area (PPA), up to 10X faster turn-around time and double-digit improvements in verification coverage, 4X faster test with the same coverage, and 4x faster analog circuit optimization when compared to optimization without the use of AI.
Synopsys has pioneered AI capabilities across the Synopsys.ai suite, adding verification, test, and analog capabilities, all commercially available and ramping. The company’s AI innovation is continuing with the development of Generative AI capabilities across the stack, starting with Synopsys.ai Copilot, and today’s announcement of a new Synopsys.ai capability for 3D design space optimization.
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Accelerating Multi-die Innovation with New 3DSO.ai for 3D Design Space Optimization, Architectural Exploration, and Silicon-Proven UCIe IP
Furthering its efforts to drive the mainstream adoption of multi-die designs, Synopsys is introducing 3DSO.ai, a new AI-driven capability delivering unparalleled productivity gains while maximizing system performance and quality of results. Built natively into Synopsys 3DIC Compiler, a unified exploration-to-signoff platform, and powered by fast integrated analysis engines, 3DSO.ai offers optimization for signal integrity, thermal integrity, and power-network design. Synopsys 3DSO.ai is now available to early adopters.
Ghazi also highlighted Synopsys’ industry-first solution for early architecture exploration of multi-die systems, Synopsys Platform Architect – Multi-Die. Platform Architect accelerates design timelines, delivering a dramatic 6-12 month “shift left” from RTL for the analysis of performance and power, while accounting for the interdependencies between multiple dies. It allows systems architects to automate modeling, simulation, and analysis for early partitioning decisions, and helps customers avoid costly, late-stage changes and respins.
Additionally, he emphasized the importance of multi-die solutions, spotlighting Intel’s Pike Creek, the world’s first silicon-proven UCIe-connected and a result of collaboration between Intel, TSMC and Synopsys. The chip, a collaboration between Intel, TSMC and Synopsys, includes an Intel UCIe IP die built on its Intel 3 process node and a Synopsys UCIe IP die built on the TSMC N3E process. Ghazi commented, “This is the future of the semiconductor industry: multiple fabs, multiple sets of industry standard UCIe IP, and modern EDA packaging solutions.”
Advancing State-of-the-Art Architectural Exploration; System Verification and Validation
During today’s keynote, Ghazi explained that as AI becomes pervasive, software plays a much larger role in semiconductor design, demanding a holistic systems approach to silicon innovation. From large, monolithic SoCs for AI workloads to new multi-die systems, the complexity and software-defined nature of today’s designs requires verification systems with higher performance and greater capacity. In this context, Synopsys unveiled two new hardware-assisted verification (HAV) solutions for faster, higher capacity emulation and prototyping.
- Synopsys ZeBu® EP2 is the latest version in the Synopsys ZeBu EP family of unified emulation and prototyping systems. Available now, the new system provides the fastest emulation and prototyping platform for AI workloads, making it ideal for software bring-up, software/hardware validation, and power/performance analysis.
- Synopsys HAPS®-100 12 system is Synopsys’ highest capacity and density FPGA-based prototyping system, with a mix of fixed and flexible interconnects and a rack-friendly design, particularly useful for prototyping big designs that require many FPGAs, such as multi-die systems and large SoCs. Available now, this new prototyping system shares a common hardware platform with Synopsys ZeBu EP2.
Together, these new offerings expand the industry’s broadest HAV portfolio, helping customers reduce design risks and ensure that increasingly complex semiconductor designs perform as intended.
SOURCE: Synopsys
