Renesas Electronics Corporation has introduced the industry’s first 650V Gallium Nitride (GaN) power device featuring dual-side cooling (DSC). Engineered specifically for high-density power conversion within 800V high-voltage DC (HVDC) AI data center architectures, the newly launched TP65H020G4PLSGBD Depletion-Mode (D-Mode) transistor delivers a class-leading 20 milliohms ($m\Omega$) on-resistance ($R_{DS(on)}$) within an ultra-compact PQFN package.
Renesas is currently providing engineering samples of the device to tier-one AI data center original equipment manufacturers (OEMs) and original design manufacturers (ODMs).
Addressing the Megawatt Power and Thermal Density Challenge
Built upon Renesas’ proprietary Gen IV Plus GaN technology platform, the device is optimized to handle the extreme power demands of megawatt-scale AI computing infrastructure supporting continuous operation up to 700V. The component primarily targets the 800V DC-to-DC intermediate bus converter (IBC) stage-which steps voltage down to 48V, 12V, or 6V-as well as the battery backup unit (BBU) and capacitor bank unit (CBU) systems housed within sidecar power racks.
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As high-density server rack power requirements escalate from standard 120 kW configurations toward megawatt capacities, physical board real estate and thermal dissipation constraints present major hurdles for system architects. Unlike traditional top-side-cooled packages, the dual-side-cooled PQFN architecture dissipates heat simultaneously through its top and bottom surfaces, reducing top-side thermal impedance by 10%. Additionally, the device’s $8 \times 8\text{ mm}$ PQFN footprint yields a 57% size reduction compared to legacy $10 \times 15\text{ mm}$ TOLT packaging.
Engineered upon Renesas’ proprietary Gen IV Plus 650V Depletion-Mode (D-Mode) Gallium Nitride (GaN) architecture, the TP65H020G4PLSGBD transistor delivers a class-leading low on-resistance of just 20 mΩ to maximize energy efficiency in high-density power conversion systems. Housed in an ultra-compact $8 \times 8\text{ mm}$ PQFN form factor featuring dual-side cooling (DSC), the package achieves a 57% reduction in printed circuit board footprint compared to legacy $10 \times 15\text{ mm}$ TOLT designs while reducing top-side thermal impedance by 10% through simultaneous top-and-bottom heat dissipation. Purpose-built for next-generation megawatt-scale infrastructure, the device optimizes 800V-to-48V, 12V, or 6V intermediate bus converters (IBC), battery backup units (BBU), and capacitor bank unit (CBU) power racks, delivering the high power density and thermal headroom required for modern high-voltage DC AI data center architectures.
The Gen IV Plus GaN process incorporates key technical advantages, including ultra-low gate charge ($Q_g$) and output capacitance ($C_{oss}$), an integrated freewheeling diode with minimal reverse recovery ($Q_{rr}$), and a high threshold voltage that operates without requiring negative gate bias. Consequently, design engineers can drive the device using standard silicon gate drivers while switching into megahertz (MHz) frequency ranges. This capability reduces passive component sizes and lowers overall bill-of-materials (BOM) costs by eliminating the need for specialized Enhancement-Mode (E-Mode) driver integrated circuits.
“Customers building megawatt-scale AI data centers are running out of board space and thermal headroom before they hit their power limits,” said John Wiggenhorn, Senior Product Line Director of High-Voltage GaN at Renesas. “With the industry’s first dual-side-cooled 650V GaN, we cool the device from both sides and cut the footprint significantly, so designers can move more power through the intermediate bus without redrawing the board or adding more cooling hardware. And because it keeps the operational simplicity of the silicon gate drive customers already use, it’s an extremely easy upgrade.”
Ecosystem Integration and Validated Silicon Performance
Defined through close collaboration with major AI infrastructure developers, the new DSC PQFN package establishes an industry-standard footprint to support multi-sourcing flexibility. When paired with Renesas auxiliary controllers, gate drivers, and microcontrollers (MCUs), the device enables a comprehensive, single-vendor power management ecosystem for hyperscalers, OEMs, and ODMs transitioning to 800V architectures.
Renesas has validated the platform through hardware testing of a 6 kW, 800V-to-48V LLC DC transformer (DCX) reference design. Controlled by a Renesas RA6T3 MCU, the system achieved a power density of 2.6 kW/in³, with full-load efficiency measuring 0.21% higher than an equivalent TOLT-packaged board. The smaller form factor also conserves printed circuit board (PCB) trace area, enabling improved layout symmetry across field-effect transistors (FETs). Additional 800V-to-12V and 800V-to-6V DC/DC IBC reference designs utilizing the $8 \times 8\text{ mm}$ DSC platform deliver similar gains in power density, efficiency, and scalability.
