At the Future of Memory and Storage (FMS) Conference, Microchip Technology, in collaboration with Micron Technology, demonstrated a high-performance, end-to-end PCIe Gen 6 storage architecture designed to meet the intensive throughput and low-latency demands of AI, high-performance computing, and cloud data center infrastructure. Built on a 3 nm process technology, Microchip’s Switchtec Gen 6 PCIe fanout switches provide high-bandwidth interconnectivity alongside hardware root of trust and post-quantum-safe cryptography. When paired with Micron 9650 NVMe SSDs the industry’s first mass-produced PCIe Gen 6 SSDs the architecture doubles PCIe Gen 5.0 bandwidth to 64 GT/s per lane to optimize data flow across compute and storage resources.
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Highlighting the ecosystem synergy, Brian McCarson, corporate vice president and GM of Microchip’s data center solutions business unit, noted, “Advancing data center performance is not solved by any single component and our work with Micron highlights the importance of taking a cohesive approach,” adding, “We’re bringing together complementary strengths in switching and storage to demonstrate how a well aligned ecosystem can enable scalable, high bandwidth architectures for next generation AI and cloud platforms.” Concurrently, Larry Hart, senior director of solutions marketing for Micron’s Core Data Center Business Unit, emphasized, “AI infrastructure is entering a new era in which storage performance and ecosystem interoperability must advance in lockstep,” underscoring how this balanced fabric enables scalable, disaggregated system designs for modern cloud platforms.
