Partnership Enhances Alphawave Semi’s PCIe 6.0 PHY and Controller Solution with Third-Party Verification and Strengthens Interconnectivity in AI Compute Infrastructure
Alphawave Semi a global leader in high-speed connectivity for the world’s technology infrastructure, announced a successful collaboration with Keysight Technologies, a market-leading provider of design, emulation and testing solutions. The interoperability between the PCIe 6.0 64 GT/s subsystem (PHY and controller) device from Alphawave Semi and the Keysight PCIe 6.0 64 GT/s Protocol Exerciser was demonstrated and a connection to the maximum PCIe 6.0 data rate was negotiated. Alphawave Semi, already on the list of PCI-SIG 5.0 integrators, will accelerate next-generation PCIe 6.0 compliance testing through this collaboration.
Alphawave Semi’s leading silicon implementation of the new PCIe 6.0 64 GT/s Flow Control Unit (FLIT)-based protocol enables higher data rates for hyperscale and data infrastructure applications. Keysight and Alphawave Semi have reached another milestone with the successful establishment of a CXL 2.0 connection, thereby laying the foundation for future cache coherence in the data center.
“Test and measurement are critical aspects of interoperability that enable Alphawave Semi to bring our products and customer solutions to market faster,” said Letizia Giuliano, Vice President of IP Product Marketing at Alphawave Semi. “We are pleased to collaborate with Keysight to accelerate the transition to 64 GT/s through Keysight’s state-of-the-art PCIe 6.0 protocol validation solution and increase confidence in our ability to provide end-to-end connectivity solutions that enable AI processing in high-performance Accelerate computing and data infrastructures.”
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“In the race to scale AI, PCIe will play a central role in connecting computing resources and efficiently processing the required workloads. This collaboration with Alphawave Semi demonstrates both companies’ commitment to developing the PCIe 6.0 standard, which anticipates the demands of high-performance computing through advances in AI and ML,” said Dr. Joachim Peerlings, Vice President of Network and Data Center Solutions at Keysight. “This will usher in a new era of connectivity that addresses the massive increase in I/O performance needed for compute-intensive applications such as generative AI.”
PCIe 6.0 marks the evolution of the ubiquitous technology from two-stage NRZ to four-stage PAM4 signaling. While this transition introduces signal integrity and new protocol challenges to ensure the necessary backward compatibility, it improves the future-proofing of the technology by implementing Forward Error Correction (FEC) over FLIT. FEC allows for higher bit error rate (BER) tolerance while achieving acceptable packet loss. The result of this collaboration was the successful demonstration of FLIT transactions (requests and completions) of payload FLITs in the silicon implementation of the PCIe 6.0 64 GT/s subsystem.
The Alphawave Semi PCIe subsystem is an ultra-power-efficient, low-latency, and highly reliable interface IP based on the industry’s most successful PAM4 SerDes IP. In AI and high-performance computing (HPC) systems where memory performance is critical, the Alphawave Semi PCIe 6.0 subsystem can be expanded to support CXL 3.0 with a PCIe and CXL controller, enabling memory coherency at the data center level.
SOURCE: BusinessWire
