Alphawave Semi’s platform of ready-to-integrate subsystem IP for 64G UCIe, 224G SerDes, 800G/1.6T UALink and UEC plus reference chiplet architecture designs will underpin future AI deployments
Alphawave Semi, a global leader in high-speed connectivity and compute silicon for the world’s digital infrastructure, is reinforcing its leadership in AI silicon connectivity with silicon-proven chiplets and IP subsystems across advanced nodes and packaging technologies. These innovations will be featured at the upcoming TSMC 2025 North America Technology Symposium.
As artificial intelligence workloads scale exponentially, next-generation data centers demand ultra-high-speed, low-latency interconnects capable of handling massive data throughput. Meeting this challenge requires deep expertise across a broad range of cutting-edge technologies—an area where Alphawave Semi continues to lead.
The company offers customized, silicon-optimized solutions built for a variety of AI workloads. These include 64G UCIe, 224G SerDes, 800G/1.6T UALink, and 800G/1.6T UEC controllers, available as silicon-proven chiplets or IP subsystems. Alphawave Semi also recently launched a new line of PAM4 and Coherent-lite DSPs, designed to support both optical and electrical links between servers and across data centers.
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By harnessing the most advanced process nodes, Alphawave Semi delivers next-gen architectures and fabrics that push the boundaries of performance and density. The company’s die-to-die (D2D) connectivity—enabled by standards such as UCIe—supports seamless chip-to-chip communication both within packages and across heterogeneously integrated data center solutions.
These ultra-optimized scale-up networks enable the integration of up to 1,000 GPUs to function as a unified compute engine. Multiple scale-up GPU clusters can then be interconnected using dedicated scale-out network channels, purpose-built to deliver low-latency, low-power, and high-efficiency data movement with minimal collisions.
“Through our unique DSP-based SerDes, manufactured using TSMC’s most advanced process nodes, our AI platform can deliver the performance required at the low-power levels needed via passive copper and low-power optical connectivity. This includes bringing optics to the XPUs and leverages the low power, high-efficiency benefits of UCIe die-to-die connectivity (below 1pJ/bit) while capturing the long reaches of optics,” said Mohit Gupta, Senior VP & GM, Custom Silicon & IP, Alphawave Semi.
“Our portfolio of silicon IP subsystems are set to be the building blocks of the custom silicon and chiplets that make up AI platforms,” continued Mohit Gupta.
“The participation of Alphawave Semi in the UALink Consortium, along with their foundational IP for AI platforms, is helping advance the high-speed connectivity essential for next-generation AI infrastructure,” said Kurtis Bowman, UALink Consortium Chair. “Their integration of low-latency controllers and high-speed SerDes technology aligns well with UALink’s mission to deliver high-bandwidth, low-latency interconnects. We believe their collaboration will play a key role in driving the scalability and efficiency required to support the rapid growth of AI workloads.”
“We are delighted with our latest collaboration with Alphawave Semi to deliver this AI platform, which is a strong example of how advanced process technology and packaging can come together to enable the next wave of AI and data center innovation,” said Lipen Yuan, Senior Director of Advanced Technology Business Development at TSMC. “We will continue to work with our Open Innovation Platform® (OIP) partners like Alphawave Semi to enable semiconductor innovation that will help shape the future of compute infrastructure.”
Alphawave Semi’s AI platform includes a comprehensive suite of standard and custom-form-factor chiplets, featuring a wide array of proven I/O chiplet technologies. The platform supports scale-up and scale-out connectivity architectures over 224G networks via co-packaged optical and electrical solutions—including third-generation 64G UCIe and UALink PHYs and controllers with ultra-low latency and power consumption.
These solutions are brought to life through a collaborative ecosystem of foundry, SerDes, connector, and component partners, leveraging TSMC’s cutting-edge 2.5D and 3D packaging, as well as advanced 2nm process nodes. The result: a flexible, scalable portfolio of AI silicon and compute subsystems ready to power the next era of intelligent infrastructure.